At what point in new product development does the solder get updated with the rest of the product or process?  “We” as an industry have just finished a “mandatory” update of soldering products, because of the European Union’s “...restriction of the use of certain hazardous substances in electrical and electronic equipment“.  Commonly called RoHS.  Where several components of the electronics we use in daily life have gone through a redesign, mostly to remove Lead.

Now that the rush is over, many of the exempt applications have been updating their designs, without trying new solders.  One example is company that I have been working with that updated their entire process with new equipment.  Because of the great rush for new equipment, this technology company has also bought new printers, placement machines, reflow ovens and x-ray machines.  They updated everything across the “board” (pun intended).  Except the solder paste that they have been using since the dawn of man.  Well, this is an exaggeration, as this particular application has always been a niche application, using a specialty solder.  But, since the inception of the product, they have been using the same material; an older formulation for which we developed a replacement flux vehicle specifically designed for the alloy that they were using.

Imagine, you purchasing one of the new “retro” muscle cars (insert your favorite…), yet still having the bias-ply tires you remember on the original.  At what point does the performance of the total package suffer from the flaws in the original design?  Something that is not directly related to the output of the car yet can have a measurable impact on the total package.

The same scenario occurred with this customer.  After they went into production with the updated process, the solder quickly became the weak link in the chain, and they called us for help.  It seems that under the old process, the board-by-board processing technique covered the flaws in the older formulation paste that was handed down from project to project, and once everything else was under control, it stood out.  This is where the “new” formulation, specifically designed for the alloy that they were using, was introduced.  And it worked.  Perfect.

So, the moral of my story is where does the solder fit in?  Is it a modern component in your modern process? Or is it bias-ply in a radial world?

More information may be found at Online Help: Indium Knowledge Base (IKB).

Ok, so it happened again. Another urgent request was brought to me for action. This time it was a customer who had performed a Red Dye Penetration test on a Ball-Grid Array (BGA) that was attached to a board using our paste. A single BGA on a single board was the evaluation (Sample size is a WHOLE other topic of conversation!) The picture is one that I took of the pad that showed no wetting. There are a number of causes of why the paste did not wet only these two pads. Including poor paste transfer, BGA contamination and board contamination.

Paste transfer is certainly an issue that is at the forefront of every BGA issue. The first issue that I think of is a contaminated stencil. If their cleaning process were incomplete or sloppy, then this would definitely cause some issues. Especially if the stencil apertures were not completely cleaned out or if the solvent used was not completely removed. Solvent left in the apertures when paste is introduced would wreak havoc on reflow. But, in this case there was sufficient paste printed, because the analysis of the solder joints confirmed that the spheres of the good joints were the same volume as the suspect BGA solder joints. Had the paste had issues with transfer efficiency, those spheres would be comparably undersized.

As with Head-in-pillow, the solder spheres on the component may also play a role in the situation, where again, the increased silver content or higher than normal oxide contamination would hinder good wetting. But, would this have shown itself as non-wetting to the pad? Probably not, but rather as head-in-pillow, or a “cold” solder joint.

So, where does that lead us? Directly to board manufacturing and storage, or direct pad contamination. Board manufacturing issues would show itself, I believe, more widespread than just two localized pads. Especially since these are regular production boards. This is the same for poor board storage, where an oxide layer had may build up on the pads. But, again, it would probably be more widespread.

Therefore, my money is on contamination. We have all been to production facilities, and very rarely do I see any of the operators using gloves. In fact, at one facility, where they were placing solder preforms by hand, we brought up the idea of using gloves. Their defect rate dropped to <1%. As a matter of fact, we do not permit the wearing of silicone bracelets, as the silicone has shown to rub off and contaminate some testing. The silicone actually prevents the wetting of the flux and solder! Even our body’s natural skin oil is an inhibitor to wetting. Which is exactly what I believe happened here.

More information may be found at Online Help: Indium Knowledge Base.

Package-on-Package (PoP) use in the SMT process is slowly creeping from a niche application into mainstream use. From experience, I know that some customers are using off-the-shelf Wireless Local Area Network (WLAN) and Bluetooth Personal Area Network (PAN) integrated into their current PCB designs. Systems that already exist suddenly become user friendly with the addition of easy Bluetooth, such as portable navigation systems or even my new motorcycle helmet.

Jim, what is the biggest issue facing the widespread use of PoP’s in the world today?

Well, Mario, it is a different process. I would say component dipping is “easier” than standard SMT into solder paste, because customers are just so accustomed to paste printing. There is also a limited material set and knowledge base for this process, so I find many people feel they are pioneering and become uncomfortable. We try to provide as much knowledge as we can up-front to shorten the learning curve.

Lets talk about the component dipping process. Can you diagram the process of PoP use in the SMT world?

There are actually two different process sequences that are mainstream.

Process “A”
-Stencil print solder paste on the entire board (this will be used for all standard SMT components and the bottom component in the PoP stack).
-Place standard SMT and bottom PoP components.
-Dip second level PoP component in PoP solder paste or flux.
-Place second PoP component on top of bottom PoP component.
-Repeat if necessary for +2 level component stacks.
-Reflow.

Thank you to Jim Hisert, Semiconductor Application Engineer for Indium Corporation. More information may be found at Jim’s Semiconductor Blog or Online Help: Indium Knowledge Base.

Head-in-pillow defects related to solder paste or flux performance are classified as Materials Issues. These include poor transfer efficiency on standard apertures, insufficient wetting (fluxing) capacity, low oxidation barrier and low activity.

The key to over coming head-in-pillow defects is to get each component sphere to contact, and stay in contact, with the soldering material, mainly the solder paste.

If the solder paste itself has poor or inconsistent transfer efficiency, then how do we know that there is even going to be contact between the sphere and the paste? Low area ratios can account for lot of the transfer issues, especially if the stencils are not electro-polished or Electro-formed (e-fab), but with that said, you must match the material set to the process and stencil design. The solder paste can cover a lot of overlap.

The second half of the solder paste equation is the fluxing action. There are three parts to this; activation, oxidation barrier and stencil / tack life. High activation is an obvious choice because this is the working part of the flux, which removes the oxides from the solder and the spheres. Oxidation barriers, such as a higher rosin content of the paste’s flux, are useful because it will protect the alloy from forming new oxide, which means there’s more activation for the component’s oxide. Also, it usually adds tack, which is a huge benefit. Because if the paste stays tacky, and the package does warp, the paste will stretch to provide a continuum, so the solder and component will be a single alloy mass upon reflow.

There are artificial ways to add an oxidation barrier and additional activation, such as nitrogen reflow or a flux / paste dipping process. Nitrogen reflow PREVENTS the formation of additional oxides during the reflow process, but does not REMOVE oxides and hydroxides already formed on the components. Flux or paste dipping are viable options because this adds activation directly on the component, rather than leaving it to chance on the board. Plus, this flux or paste can be used for rework on the back-end as well.

Of course, Material solutions can overcome both the Supply and Process Issues.

More information may be found at Online Help: Indium Knowledge Base.

Head-in-pillow defects caused by on-line processing issues are categorized under Process Issues. These include printing, placement and reflow.

Printing issues not directly related to the properties of the solder paste are poor registration, imperfect or improper printer setup and poor stencil design. Poor registration leads to printing off-pad or pump-out, and is only part of the printer setup. Printing too fast or too slow will alter the amount of solder that is printed, as well as pulling paste out of the apertures (scooping). Stencil design is probably the most important of the process issues, as a bad stencil design can lead to insufficient solder deposits, which can cause the component to not even touch the paste as well as not having enough flux to overcome the oxide on the sphere or in the paste. Area ratio plays huge role, as well as transfer efficiency.

Placement is another danger zone, as offset or off-plane placement can affect head-in-pillow. As well as the placement pressure and down stop, which if the component doesn’t sit far enough into the paste, and just floats, then not all the spheres may be touching the paste.

The majority of the head-in-pillow comes from the reflow process. This is where the warping of the component actually lifts one edge, opposite edges (“Pringle effect” or “potato chip”) or even the corners or center spheres. This is why it is important to read the component manufacturer’s recommendations, so the reflow temperature doesn’t exceed the maximum processing limitations. This was brought to light to us as a OEM called us and said that they had seen a reduction in head-in-pillow because when they switched pastes, we recommended a lower peak because they were running really hot, and we reviewed the components’ ratings, and they had been running too hot for many years! Another issue in reflow is flux exhaustion, where the flux loses its activation because the reflow profile is too long. And I’ve seen them as long as 15 minutes!

Seriously, process issues are where the majority of the head-in-pillow defects are caused, but can be minimized through careful process setup.

More information may be found at Online Help: Indium Knowledge Base.

Head-in-pillow defects caused by everything before the components go on-line can be grouped into Supply Issues. Some specific issues within this group are oxidation, hydroxidation and silver segregation.

Oxidation is the most known. This is where during the manufacture, packaging, shipment or storage of the bumped components, these bumps have formed a hard-to-solder oxide coating on their surface. This is wrongly called “Black Ball” because the surface oxidation coating is not always dark, and on the flip side, dark sphere are almost always not hard-to-solder. Poor air introduced into the manufacturing, un-sealed packaging or in the storage of the components contributes to this surface oxidation.

Hydroxidation, a little less well known, is when a surface hydroxide is formed, but is usually limited to the manufacturing process as it is commonly caused by the molten spheres exposed to higher humidity. Hydroxidation is extremely hard-to-solder.

Another issue that we have seen at customers is called “silver segregation”. At this particular customer, the head-in-pillow was such a problem, that the components were sent for analysis, and the soldering surface of the sphere was found to be 36% silver. The actual causes of the silver segregation have still a mystery to me, but my thoughts are leaning towards the manufacturing of the sphere, particularly the cooling rate. The attached picture is actually of that issue, where a “silver tail” has formed on the sphere, much like a tin whisker.

Supply type head-in-pillow defects are something that we look for when addressing customers, but are usually outside Indium’s sphere of influence. (Pun intended, ha!)

More information may be found at Online Help: Indium Knowledge Base.

I know it’s been a while since my last post, but we’ve been so busy. In fact, one such incident was yesterday. One of our VP’s came to me and asked me to do a 10-15 slide presentation on head-in-pillow defects (Also called “Hidden Pillow” or Ball-in-Cup (BIC) defects). Sure, no problem. So, last afternoon, we’re on a conference call with a MAJOR OEM, and he announces “Here to speak about Head-in-pillow, is our Application Engineer, Mario…” Let’s talk about SURPRISE.

Well, my torture is your benefit…

Head-in-pillow is the incomplete wetting of the entire solder joint or a Ball-Grid Array (BGA) or Chip-Scale Package (CSP), or even a Package-On-Package (PoP). From cross-sections, it actually looks like a head has pressed into a soft pillow.

Two issues, poor wetting and component warpage cause head-in-pillow defects. They both look the same, but you can identify them because random head-in-pillow defects are from poor wetting and edge or center defects are from warpage.

I have separated all the head-in-pillow defect types into three areas. These are Supply Issues, Process Issues and Material Issues. They can be defined like this:

Supply issues are everything before you put them on the line. This includes oxidation, or any other oxidation/hydroxide effects.

Process Issues are everything that is on-line. Including printing, placement and reflow.

Material Issues is everything that has to do with the soldering itself, such as wetting capacity or flux exhaustion.

I will go in depth with each one of these issues in further posts.

More information may be found at Online Help: Indium Knowledge Base.

It seems that the topic of Halogen-Free Solder Paste has grown by another leap and bound. The big confusion is what are the definitions of Halogen-Free Solder Paste. I mean, who decides what techniques to use for the determination of Halogen-Free Solder Paste. The different testing and procedures come from many sources, including the IPC and individual Original Equipment Manufacturers (OEM’s). So, lets take a few minutes and discuss not the techniques used for testing Halogen-Free, but the procedures and reporting specifications. For procedure references, please check original post, Halogen-Free Solder Paste.

The first specification that comes my mind, is the IPC’s “J-Standards” or J-STD. The section of the J-STD that covers the halogen and halide specifications is J-STD-004. The current revision “a” states that the halogen and halide content is tested on the reflowed solder paste, by Ion Chromatography. Here is the IPC’s test method IPC-TM-650 2.3.28.1. As we have discussed in the past, Ion Chromatography is good for testing ionic halides, but may miss the covalent halogens, and of course any volatiles that contain halogens and halides. It is by this method, that some solder paste that are indeed halogen containing, can still advertise themselves as halide-free per J-STD-004. I’m not going into details about the procedure, but it involves a molten solder pot, a Petri dish, and a plastic bag. Sound very scientific to you? Me neither; more like a 9th grade science fair project. By the way, the IPC’s definition of Halide-Free is <0.05% (500ppm) total halides. No mention of halogen-free.

Another specification that is preferred by some OEM’s states that a test board be printed with solder paste, then reflowed and tested by Ion Chromatography. At least this is board-level testing, but the definition of halogen-free versus halide-free remains, as well as their definition of halide-free, <0.09% (900ppm). I have personally tested pastes to this specification, and on one test, knowing that there is >0.5% (5000ppm) total halogens in the sample of the raw flux, have it come back on this test as <0.001% (10ppm). Knowing this is not bad, if only based on the fact that the halide-containing activators may have burned away.

Lets get into the big-ticket topic; “no intentionally added halogens”. One of the only test methods of determining total halogen content is Parr Oxygen Bomb, then ion chromatography of the ash, on the raw solder paste or flux. This will give you both the halogen and halide content of the flux vehicle. It is no secret that some OEM’s looking into truly halogen-free solder pastes, after testing that has showed that their “halide-free” per J-STD-004) pastes that they are using now, is failing due to corrosion or dendritic growth. The statement “no intentionally added halogens” sums it all up, where in reality, only the naturally halogen-containing compounds would be detected, such as the rosin. Even on the post-reflow flux residue, ion chromatography may still miss the covalently bonded halogens, but not oxygen bomb testing.

More information may be found at our Online Help: Indium Knowledge Base.

For the second half of Solder Paste Transfer Efficiency, I would like to talk about tolerances and the Rule of 10% Standard Deviation (σ). From part one, we have a target height of 0.005” (5 mils), which is the stencil thickness. Therefore we assume for this application 5 mils is 100%.

We can now calculate the Capability Indices of the for the various ultra-fine pitch components using the Standard Deviation of the ratios. In the picture to the right, we have reasonable print tolerances, which are plus or minus one-half of the 5 mil thickness; or 2.5-7.5 mils. Using the Rule of 10%, the tolerance for 10% standard deviation could be used to characterize the solder paste prints (until further process measurement shows otherwise).

So lets calculate the Upper and Lower Spec Limits (USL & LSL):

LSL = (Ratio) x (Nominal Height) = (50%) x (0.005”) = 0.0025”

USL = (Ratio) x (Nominal Height) = (150%) x (0.005”) = 0.0075”

If the LSL is 0.0025” and USL is .0075”, then we can calculate the upper and lower Capability Indices, for 6 Standard Deviations (6 sigma):

Cpu = (Height % – 50%) / (3 x Std. Dev.) = (100-50) / (3 × 10) = 50 / 30 = 1.7

Cpl = (150% – Height %) / (3 x Std. Dev.) = (150-100) / (3 × 10) = 50 / 30 = 1.7

Cpk = (Cpu + Cpl) / 2 = 1.7

As far as I’m concerned a Cpk of 1.7 is acceptable, but the measured average height will indicate whether we need to make the tolerances higher or lower. A wider tolerance will give you a higher Cpk, but again, a Cpk just below 2.0 will be easier to monitor. It is common knowledge that no matter what you use for your Cpk (as long as its tracked), it will go down when your process is losing control and up when it gets better (or your measurement system has been compromised).

To maximize the Cpk; a good stencil printer cleaning, new squeegee blades and better board support will make marked improvements. Starting with these features not only takes a lot of the variation out of the process, but will give you a better baseline.

Again, thanks to Chris Anglin for his help on this posting.

More information may be found at our Online Help: Indium Knowledge Base or Chris Anglin.

A great Indium Knowledge Base question came from a customer last week for “recommendations on solder paste height versus component pitch…” Well, the first thing I did was go to our solder paste transfer efficiency and process guru Chris Anglin, and this is what we’ve come up with.

Typically, it is the variation in solder paste deposits during ultra fine pitch component assembly that are measured, and the amount of variation can be observed as an indicator of defect level. The consequence of excessive variation is that ultra fine pitch defect levels tend to be most susceptible.

Because there is no single answer for all applications, we must look at the customers’ individual processes. Only then the upper and lower specification limits can be defined. So, our initial recommendation, therefore, institute a 5S Methodology practice at the paste print workstation to minimize the root causes for the variation in the paste deposition process. This is to recognize the amount of variation in, for example, solder paste height, eliminating the variation due to all other causes outside the actual printing process. This, by the way would make a great DOE and 6σ Green Belt project, for only through the paste measurement and number crunching in your favorite statistics program, can the variation of the paste heights be put into a number. And, we are not talking about ten boards, here… The minimum amount of boards that I usually start with is about 100 boards. Now, I know that not everyone can get 100 clean, fresh boards to test with, so I have about 20 boards that are reused, cleaning them in a commercially available stencil and board washer.

It is often easy to identify root causes for variation after 5S is instituted. Some of the more common causes for variation are related to board support and squeegees. As control of these basic features of the solder paste deposition process is improved, the variation in solder paste height will be minimized, and defect levels will decrease for the ultra fine pitch components.

Indium Corporation’s Technical Service has some detailed reports from our Process Simulation Lab that we have done to show the typical variations in solder paste deposition across different apertures and stencil types.

More information may be found at our Online Help: Indium Knowledge Base or by contacting our Chris Anglin.