Papers by Amanda Hartnett
by Amanda Hartnett , Jacques Matteau , Ronnie Spraker, Omar Knio
As semiconductor processing has moved to 300mm wafers, the size of
deposition targets, including tungsten, tantalum, and molybdenum has grown,
and process complexity has increased as well. This added size and complexity
contributes to the stress on a target assembly during the physical vapor deposition
(PVD) process, and the target assembly’s ability to withstand this stress has
a large effect on the resulting deposition rates, yields, and film properties.
One of the major sources of stress is the coefficient of thermal expansion
(CTE) mismatch between metal targets in semiconductor processes, such as
tungsten (CTE of 4.5*10-6/°C), tantalum (6.5*10-6/°C), and molybdenum
(5.1*10-6/°C) compared with their backing plates, which are typically made
of aluminum (23*10-6/°C), brass (21.2*10-6/°C), or copper-chrome (17.6*10-
6/°C). Standard soldering and solid state joining processes have difficulty
controlling stress produced by the CTE-mismatch. We will demonstrate how the
NanoBond® process can be used to control stresses during the bonding and
deposition processes. Modeling will be conducted to compare standard bonding
processes to the NanoBond process, accounting for CTE mismatches.
SVC Tech Con 2011, NanoFoil, NanoBond, sputtering target, CTE mismatch
[Permanent Link to this Paper ]
Posted on 19 Apr 2011
by Amanda Hartnett , Daniel Evans Jr., Don Beck, Seth Homer
High-power semiconductor devices, such as high-brightness LEDs, must be mounted using a robust die-attach material that can handle the temperature fluctuations generated by the chip and mechanical stresses due to CTE mismatches between the die material and substrate to which it is mounted. The selected material must also comply with current legislation, which restricts manufactured products containing numerous materials due to environmental concerns, including some that were historically popular in this application. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented.
Utilizing Palomar Technologies’ die bonder, AuSn solder preforms and solder paste will be placed/dispensed and reflowed using a Pulse Heat System (PHS). Evaluation methods comparing these means of eutectic die-attach to a pre- plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test method as well as hypotheses of results.
gold-tin solder, LED, die bonder, solder preforms, solder paste, automated pick-and-place, eutectic die-attach, solder spread
[Permanent Link to this Paper ]
Posted on 14 Oct 2011
by Steve Buerki, Amanda Hartnett
Paper Interview
Process and Reliability Advantages of AuSn Eutectic Die-Attach
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High-power semiconductor devices must be mounted using a robust die-attach material that can handle the temperature fluctuations generated by the chip and mechanical stresses due to CTE mismatches between the die material and the substrate it is mounted to. Traditionally, various die-attach products, such as metal-filled conductive epoxies, high lead-containing solders, and gold-silicon solders, have been sufficient to mount the chip and have it perform reliably for the life of the device it operates. However, the trend toward increasing heat generation, the demand for compact devices, the enactment of RoHS and REACH legislation, and the transition to GaAs chips, limit the use of conventional materials. The demand for high reliability in power devices, in light of these industry trends, has led engineers to evaluate various new materials for their die-attachment.
The use of a high temperature solder preform is proposed and demonstrated for use as a die-attach material in high power devices. The suggested solder preforms are eutectic gold-tin and may be implemented for high volume or lab quantity adoption using a Palomar Technologies’ die bonder. This equipment is capable of handling the complete die-attach process, including high-accuracy pick-and-place of substrates, eutectic gold-tin preforms, and components; eutectic die-attach; and pulsed-heat reflow using a computer controlled Pulse Heat Stage (PHS). Each of these steps is precisely controlled to offer a near void-free eutectic die-attach between the device and its substrate. This is critical for thermal and electrical stability in high power applications. When the substrates, preforms, and components are supplied in high volume packaging, the assembly line can be fully automated, which enables a reduction in the cost of ownership and improves process yields.
Assembly applications suited for this process include, but are not limited to, high-brightness LEDs, power amplifiers, LASER diodes, VCSELS, lid attach, MEMS, RF packages, IGBT modules and wafer scale packaging.
wafer scale packaging, pb-free, eutectic die-attach, automated pick-and-place, solder preforms, die bonder, AuSn solder
[Permanent Link to this Paper ]
Posted on 5 Nov 2009
by Amanda Hartnett , Dr. Ronald C. Lasky , Timothy Jensen
Chinese version of Soldering Challenges in a Halogen-Free PCB Assembly Process
halogen-free, halide-free, solder, soldering, graping, flux, head-in-pillow, hole-fill, CHINESE LANGUAGE
[Permanent Link to this Paper ]
Posted on 13 May 2011
by Timothy Jensen , Dr. Ronald C. Lasky , Amanda Hartnett
Flame retardants have played an important role in the safety of many products. It is safe to say that thousands of lives have been saved by flame retardants. Flame retardants are used in products as varied as children's pajamas to electronics assemblies. Some of the more successful flame retardants are halogenated compounds. Halogenated materials are found in polyvinyl chloride (PVC), brominated flame retardants (BFRs), chlorinated flame retardants (CFRs), as well as in fluxes used in the electronics assembly industry. Product does not contain any halogenated compounds. However, that is not exactly how the term is used for soldering fluxes. A flux that is classified as
halide-free by the IPC/J-STD-004 is actually only free of ionic halides.
hole-fill, head-in-pillow, flux, graping, soldering, solder, halide-free, halogen-free
[Permanent Link to this Paper ]
Posted on 10 Mar 2010
by Amanda Hartnett , Dr. Ronald C. Lasky
The element indium is an ideal thermal interface material (TIM) for heat dissipation in many of today’s very fast, very hot integrated circuits. Its key advantage is its high bulk thermal conductivity, but other attributes include a low tensile strength and indium’s ability to lower melting temperatures when alloyed with other elements.
TIM, indium
[Permanent Link to this Paper ]
Posted on 10 Mar 2010
