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Papers by David Sbiroli

• Specification Limits Review for Solder Paste Stencil Print Inspection (SPI)

  by Chris Anglin, David Sbiroli, Ed Briggs

  The continual miniaturization of electronics components for personal electronics devices, coupled with the conversion to RoHS- and REACH-compliant lead-free assemblies, has put a tremendous strain on the electronics assembly industry. Introduction of 01005 passives, and active components on the order of 0.3mm pitch, initiates newly defined questions about specification limits for solder paste stencil print performance.

  This paper discusses variability of solder paste print performance and its relationship to specification limits. The objective is to describe analyses to determine stencil print process character, using actual paste print measurement data. Aside from setting specification limits, application of statistical methods for the analysis of variation in stencil print performance could help understand appropriate production statistical process control (SPC) limits sought by SMT manufacturing and quality engineers from stencil print inspection results that are gathered during SMT assembly.

  Effects on values of Cp and Cpk by various specification limits are presented. This discussion is based on recent application development experiments, to elucidate how average solder paste measurement and standard deviation measurement effect new print process capability challenges. From this work, a strategy to optimize a new 01005 stencil printing process is reviewed. Importantly, the discussion includes key factors with planning quality aspects of SMT assembly. SPC techniques presented will show how to measure stencil print performance capability, and result in opportunity for reduced assembly costs and increased sales income.

  transfer efficiency, process capability study, capability ratio, statistical process control (SPC), control charts, stencil aperture design, pad design, solder paste, area ratio

  [Permanent Link to this Paper]

  Posted on 24 Jan 2011

• Sustaining a Robust Fine Feature Printing Process

  by George Babka, David Sbiroli, Richard Brooks, Chris Anglin

  With the introduction of 01005 chip components and 0.3 mm pitch CSP devices, electronic component packaging is pushing surface mount technology to the limits of its potential. Miniaturization is driving the electronics industry to implement the smallest and tightest pitch components in order to meet their customer demands. But how much miniaturization is possible before there is a paradigm shift in the technology? At what point is solder paste no longer viable? How small of a feature can be printed with solder paste, and can this process be implemented into a production environment?

  Most of the factors and critical parameters in ultra-fine pitch printing have been well understood and documented for over twenty years. Some of these parameters are squeegee speed, squeegee pressure, stencil design (technology, thickness & area ratio), and solder paste. But as the pitch and aperture sizes get smaller and smaller, we begin to see that additional factors start to have an increased effect on the solder paste deposition (transfer efficiency). What are these factors and can we control them in order to obtain acceptable results for transfer efficiency and minimized variability? This paper will evaluate these additional factors and how they affect the transfer efficiency of the paste.

  ultra-fine pitch printing, separation speed, stencil technology, stencil design, pad design, solder powder, tooling, solder paste, area ratio

  [Permanent Link to this Paper]

  Posted on 15 Oct 2009

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