Papers by Ed Briggs
by Brook Sandy , Ed Briggs , Dr. Ronald C. Lasky
The increased function of personal electronic devices, such as mobile phones and personal music devices, has driven the need for smaller and smaller active and passive components. This trend toward miniaturization, occurring at the same time as the conversion to RoHS-compliant lead-free assembly, has been a considerable challenge to the electronics assembly industry. The main reason for this is the higher reflow process temperatures required for Pb-free assembly. These higher temperatures can thermally damage the PCB and the components. In addition, the higher reflow temperatures can negatively affect the solder joint quality, especially when coupled with the smaller paste deposits required for these smaller components. If additional thermal processing is required, the risk increases even more.
bismuth, bismuth based alloys, low temperature soldering, pb-free, delamination, lead-free
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Posted on 6 Jun 2011
by Ed Briggs , Dr. Ronald C. Lasky
Chinese version of Best Practices Reflow Profiling for
Lead-Free SMT Assembly.
CHINESE LANGUAGE, graping, head-in-pillow, Voids, solder balling, solder beading, tombstoning, reflow profile, solder defects
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Posted on 22 Mar 2010
by Dr. Ronald C. Lasky , Ed Briggs
The combination of higher lead-free process temperatures, smaller print deposits, and temperature restraints on electrical components has created difficult challenges in optimizing the reflow process. Not only are the electronic components and the PWB at risk, but the ability to achieve a robust solder joint becomes difficult, especially if the PCB is thermally massive. In addition, the constant miniaturization of electronic components, hence smaller solder paste deposits, may require the use of smaller particle-sized powders. Both the small solder paste deposits and small particle size result in a large surface area-to-volume ratio that challenges the solder paste's flux to effectively perform its fluxing action. The possible resulting surface oxidation can lead to voiding, graping, head-in-pillow, and other defects. Smaller components are also more susceptible to tombstoning and defects related to solder paste slump.
This paper is a summary of best practices in optimizing the reflow process to meet these challenges of higher reflow temperatures, smaller print deposits, decreased powder particle size, and their affect on the reflow process. It also discusses trouble-shooting of the most common defects in lead-free reflow, such as tombstoning, solder beading/balling, residue discoloration, voiding, graping, and head in pillow.
solder defects, reflow profile, tombstoning, solder beading, solder balling, Voids, head-in-pillow, graping
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Posted on 1 Jun 2009
by Chris Anglin, Dr. Ronald C. Lasky , Ed Briggs
Chinese version of Fine Feature Stencil Printing 0.3MM Pitch Components
miniaturization, stencil printing, solder paste, CHINESE LANGUAGE
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Posted on 13 May 2011
by Chris Anglin, Dr. Ronald C. Lasky , Ed Briggs
The explosive growth of personal electronic devices such as mobile phones and personal music devices has driven the need for smaller and smaller passive and active electrical components. Not too long ago, 0401 (40 x 10 mils) passives were seen as the ultimate in miniaturization, but recently 0201 and now 01005 passives have arrived, with rumors of even smaller sizes to come. For active electrical components, the 0.4mm pitch component has become commonplace with 0.3mm already in the works. What effect does this miniaturization have on the stencil printing process? Can it meet the challenge? This paper takes a preliminary look at some of the work that has been performed to evaluate the capability of the stencil printing process to print these fine feature components. Discussed is the stencil printing of the small features and efforts to obtain consistent volume in the printed solder paste deposit.
miniaturization, stencil printing, solder paste
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Posted on 4 Mar 2010
by Chris Anglin, Dr. Ronald C. Lasky , Ed Briggs , Timothy Jensen
The explosive growth of personal electronic devices, such as mobile phones and personal music devices, have driven the need for smaller and smaller active and passive electrical components. Not too long ago, 0401 (40 x 10 mils) passives were seen as the ultimate in miniaturization, but recently 0201 and now 01005 passives have arrived, with rumors of even smaller sizes to come. For active components, the 30 mil CSP (a chip scale package with the solder balls on 30 mil (0.75mm) centers) has become virtually a requirement for enabling the many features in modern portable electronic devices. The more than 1 billion mobile phones assembled in 2008 will use the lion’s share of the 12 billion or so CSPs concurrently manufactured.
This miniaturization trend occurring at the same time as the conversion to RoHS compliant lead-free assembly has put a considerable strain on the electronic assembly industry. This paper will discuss some of these challenges and the work that has been performed to mitigate them. Among the challenges discussed are stencil printing the small features and obtaining consistent volume in the printed solder paste deposit, minimizing the oxidation of the solder powder in the small deposit during reflow, and assuring a good finished solder joint after the reflow process.
area ratio, Print Study, Fine Powders
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Posted on 4 Mar 2010
by Dr. Ronald C. Lasky , Ed Briggs
In order to meet the European directives, WEEE (Waste Electrical and Electronic Equipment, effective Aug 2005) and RoHS (Restriction of Hazardous Substances, effective July 2006), high tin-containing alloys have entered the market as
lead-free options . For surface mount technology, the more popular of these high tin options are the SAC alloys (Sn/Ag/Cu). Unfortunately, SAC alloys have a higher melting point and exhibit poor wettability compared to Sn/Pb eutectic alloys.
[Permanent Link to this Paper ]
Posted on 4 Mar 2010
by Harish Gadepalli, Rangaraj Dhanasekaran, Dr. S. Manian Ramkumar, Timothy Jensen , Ed Briggs
Quad Flatpack No lead (QFN) packages have become a popular choice in electronics packaging due to its small form factor. They are also gaining rapid industry acceptance because of its excellent thermal and electrical performance. The bottom side of the QFN package has a large thermal pad. This exposed die attach pad effectively conducts heat to the PCB and also provides a stable ground connection. Effective soldering of this surface to the pad on the PCB is required for good thermal dissipation and component functionality. The exposed thermal pad presents various challenges during the surface mount assembly process. One major challenge is solder void formation. Voids are primarily formed due to the entrapment of volatiles in flux outgassing during the reflow process.
The primary objective of this study is to determine optimal parameters to minimize void formation in QFN packages (QFN16 and QFN20), specifically the reflow profile, leadfree solder paste and stencil aperture opening for the thermal pad. A systematic DOE based approach was used to arrive at conclusions, using the ratio of void volume on the thermal pad to the actual volume of solder paste printed as the response variable. Various graphs are presented to understand the impact of different parameters. Interaction graphs were used to determine optimal settings for each parameter.
reflow profile, lead-free, voiding, solder paste
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Posted on 21 Jan 2011
by Dr. Ronald C. Lasky , Ed Briggs
The explosive growth of personal electronic devices, such as mobile phones and personal music devices, has driven the need for smaller and smaller active and passive electrical components. Not too long ago, 0401 (40 x 10 mils) passives were seen as the ultimate in miniaturization, yet the introduction of 0201’s and most recently 01005 passives has occurred. For active components, area array packages with 0.4mm lead spacing have become virtually a requirement for enabling the many features in modern portable electronic devices, with 0.3mm packages already on the way.
This miniaturization trend, occurring at the same time as the conversion to RoHS compliant lead-free assembly, has put a considerable strain on the electronic assembly industry. This paper will discuss the specific challenge of the Graping Effect and the work that has been performed to mitigate this phenomenon. Discussed are the effects of the solder paste material attributes, consistent stencil printing of the small solder paste deposits required, and minimizing oxidation of the small solder paste deposit during reflow. All of these steps are necessary to assure a good finished solder joint.
solder paste, graping, oxidation, stencil printing
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Posted on 21 Jan 2011
by Chris Anglin, David Sbiroli, Ed Briggs
The continual miniaturization of electronics components for personal electronics devices, coupled with the conversion to RoHS- and REACH-compliant lead-free assemblies, has put a tremendous strain on the electronics assembly industry. Introduction of 01005 passives, and active components on the order of 0.3mm pitch, initiates newly defined questions about specification limits for solder paste stencil print performance.
This paper discusses variability of solder paste print performance and its relationship to specification limits. The objective is to describe analyses to determine stencil print process character, using actual paste print measurement data. Aside from setting specification limits, application of statistical methods for the analysis of variation in stencil print performance could help understand appropriate production statistical process control (SPC) limits sought by SMT manufacturing and quality engineers from stencil print inspection results that are gathered during SMT assembly.
Effects on values of Cp and Cpk by various specification limits are presented. This discussion is based on recent application development experiments, to elucidate how average solder paste measurement and standard deviation measurement effect new print process capability challenges. From this work, a strategy to optimize a new 01005 stencil printing process is reviewed. Importantly, the discussion includes key factors with planning quality aspects of SMT assembly. SPC techniques presented will show how to measure stencil print performance capability, and result in opportunity for reduced assembly costs and increased sales income.
transfer efficiency, process capability study, capability ratio, statistical process control (SPC), control charts, stencil aperture design, pad design, solder paste, area ratio
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Posted on 24 Jan 2011
by Chris Anglin, Ed Briggs
This paper is a summary of best practices in optimizing the printing process focusing on comparison of large and small apertures, square vs. round, not with the same area ratio but with similar or the same volume. This paper will definitively clear the air on the round versus square aperture debate.
SMT, circuit board assembly, stencil apertures, solder paste, stencil printing
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Posted on 21 Jun 2011
