White Papers

Indium Corporation conducts extensive research on the soldering fundamentals for Surface Mount Technology and other electronics applications.

Browse our library for abstracts of some of the most popular published articles that you may find useful in your efforts to improve your process results. All papers in our library are available for download.

Check the box next to each paper you want to download. You may download as many papers as you wish. After selecting papers and completing the contact information form on this page, the paper(s) will be e-mailed to you at the e-mail address you provide.

    Papers by Seth Homer

  • Evaluation of Test Protocol for Eutectic Die-Attach Using High Power LEDs

    by Amanda Hartnett, Daniel Evans Jr., Don Beck, Seth Homer

    High-power semiconductor devices, such as high-brightness LEDs, must be mounted using a robust die-attach material that can handle the temperature fluctuations generated by the chip and mechanical stresses due to CTE mismatches between the die material and substrate to which it is mounted. The selected material must also comply with current legislation, which restricts manufactured products containing numerous materials due to environmental concerns, including some that were historically popular in this application. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented. Utilizing Palomar Technologies’ die bonder, AuSn solder preforms and solder paste will be placed/dispensed and reflowed using a Pulse Heat System (PHS). Evaluation methods comparing these means of eutectic die-attach to a pre- plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test method as well as hypotheses of results.

    gold-tin solder, LED, die bonder, solder preforms, solder paste, automated pick-and-place, eutectic die-attach, solder spread

    Posted on 14 Oct 2011

  • Minimizing Voiding in QFN Packages Using Solder Preforms

    by Seth Homer, Dr. Ronald C. Lasky

    According to Prismark Partners, the use of quad-flat no-leads (QFNs) is growing faster than any package type except for flip-chip CSPs. Prismark projects that by 2013, 32.6 billion QFNs will be assembled worldwide, which represents 15% of all IC packages.

    However, QFNs can be a challenge to assemble, especially when it comes to voiding. In most QFN assembly processes, solder paste is used as a means of attachment. This approach can be problematic, as excessive voiding often occurs due to the lack of standoff on the component and the high flux content of the paste. The addition of a solder preform can reduce such voiding by increasing the solder volume of the joint without adding flux volume.

    Adding preforms to an assembly process is very easy. Preforms are packaged in tape & reel for easy placement by standard pick and place machines, right next to your components. The focus of this paper will quantify the preform requirements and process adjustments needed to use preforms in a standard SMT process. In addition, experimental data showing void reduction using preforms will also be presented.

    Apex 2012, solder preforms, flux, QFN packages

    Posted on 14 Oct 2011

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