Papers about Apex 2011
by Gordon Clark, Renee Michalkiewicz, Timothy Jensen , Brian Toleno, Jasbir Bath
Over the last few years, there has been an increase in the evaluation and use of halogen-free soldering materials. In addition, there has been increased scrutiny into the level of halogens and refinement of the definition and testing of halogen-free soldering materials. The challenge has been that there has been no common standard across the industry in terms of halogen-free definitions and the corresponding test methods to determine these. This has created confusion in the industry as to what end users want and what soldering materials suppliers can actually provide. This paper will review the status of both halogen-free and halide-free in terms of definitions, test methods and the limitations and accuracy of test methods used to determine if a soldering material is halogen/halide-free or not. For halogen-free and halide-free definitions, the paper will review the different industry standards which are currently available and those being drafted, and it will discuss any similarities and differences. It will also cover the origins of some of the definitions mentioned in the standards. The paper will include a review of the accuracy and limitations of several test methods and preparation techniques for halogen and halide determination.
Apex 2011, soldering materials, halides, halogen-free
[Permanent Link to this Paper ]
Posted on 11 Apr 2011
by Dr. Ronald C. Lasky , Paul Socha , Carol Gowans
Although many have predicted the demise of through-hole components, they
are alive and well with tens of billions assembled each year. In many cases
these components are assembled by wave soldering. However, in many mixed
product technology (i.e. SMT and through-hole on the same board) products,
it makes sense to consider assembling the through-hole components with the
pin-in-paste (PIP) process. PIP has been successfully used for several decades
now; however in many cases it is not possible to print enough solder paste to
obtain an acceptable solder joint. In addition to this “solder starved” condition,
the large quantity of solder paste used to form the though-hole joint results in
excess residual flux. This residual flux can lead to difficulties in in-circuit testing
and potential surface insulation resistance concerns.
In light of the above need, solder preforms have been developed. These slugs of
solder typically come in the same sizes as 0402, 0603, and 0805 passive components.
The solder preforms are placed by the component placement machines
onto the solder deposit. This additional solder assures that an adequate solder
joint is formed with a minimum of solder paste and its residual flux.
Although PIP was an early application of solder preforms, more recently other
“solder starved” applications have emerged such as radio frequency (RF)
shields and connectors. In addition, the use of ultra thin stencils in the assembly
of miniaturized components can result in some other components being solder
starved and, hence are candidates for solder preforms.
This paper will cover the design and assembly techniques for using of solder
preforms in the “solder fortification™” needs described above. Several successful
applications will be presented. In some of these applications, defects were
reduced by 95% after implementing solder preforms.
Apex 2011, solder starvation, flux, PIP, pin-in-paste, through-hole, SMT, solder fortification, solder paste, solder preforms
[Permanent Link to this Paper ]
Posted on 11 Apr 2011
by Mario Scalzo , Todd O'Neil
Although many predicted the demise of through-hole components, they are alive and well with tens of billions used each year. In mixed SMT/through-hole PCBs, through-hole components, and especially connectors, are often used for their mechanical robustness. A typical example would be a USB connector in a laptop PC. Typically an SMT connection just doesn't have the mechanical robustness needed to support multiple connector plug-in and removals. However, performing a full wave soldering process to assemble a few through-hole components on a mostly SMT PCB doesn't usually make economic sense and may damage the PCB. In such situations, the best option is often to assemble the through-hole components and connectors with a selective soldering process.
This paper touches on identifying favorable flux properties, down-selecting low solids fluxes for lead-free selective wave soldering, the selective soldering process itself, and testing criteria. Topics reviewed will be the flux selection, optimizing the selective soldering process by varying the flux concentration, pre-heat parameters, soldering temperatures, and dwell time. The paper will finish with a summary of the work and a systematic process to select a flux and optimize the selective soldering process for high yields and quality.
flux, pb-free, lead-free, selective soldering, SMT, through-hole, PCB assembly, Apex 2011
[Permanent Link to this Paper ]
Posted on 11 Apr 2011
by S. Manian Ramkumar Ph.D., Rita Mohanty Ph.D., CEMA, Chris Anglin, Toshitake Oda
The demand for product miniaturization, especially in the handheld device
area, continues to challenge board assembly industry. The desire to incorporate
more functionality while making the product smaller continues to push board
design to its limit. It is not uncommon to find boards with castle like components
right next to miniature components. This type of board poses special
challenge to the board assemblers as it requires wide range of paste volume
to satisfy both small and large components. One way to address the printing
challenge is to use creative stencil design to meet the solder paste requirement
for both large and small components. Example of stencil design includes step
stencil, dual printing, over size aperture, etc. Stencil printing process at its
most basic level involves pushing solder paste through a stencil (with various
size apertures) by a squeegee blade. As the squeegee blade and the stencil
are in constant contact with the paste during the printing process, their surface
characteristics play an important role in the printing process. The most
important attribute of a stencil is its release characteristic. In other word, how
well the paste releases from the aperture. The paste release in turn depends on
the surface characteristics of the aperture wall and stencil foil surface. Recent
introduction of a new technology, Nano-coating for both stencil and squeegee
blades, has drawn the attention of many researchers. As the name implies,
Nano-coated stencils and blades are made by conventional method such as
laser cut or Electoform then coated with nano functional material to alter the
surface characteristics. This study will evaluate nano-coated stencils for passive
component printing including 01005. Various print experiments will be
conducted using different stencil technology, stencil thicknesses, aperture size,
aperture orientation, aperture shapes, and selected paste type with optimal
print parameters, to understand the effect of chosen factors on the print quality.
Print quality will be determined by visual inspection and 3D measurement of
the paste deposit to understand the volume transfer efficiency.
Apex 2011, solder paste, transfer efficiency, area ratio, stencil technology, broadband printing, nano-coated stencil
[Permanent Link to this Paper ]
Posted on 11 Apr 2011
by Eric Bastow
With the predominance of no-clean soldering processes and ever decreasing component standoff, the industry has had to consider the reliability of, what may be, partially activated or "gooey" flux residues under component bodies. Similarly, questions have also risen about the reliability of flux residues resulting from the reflow of no-clean solder pastes that are "entrapped" under RF shields or "cans", where escape of the volatile ingredients of the flux is greatly hindered. In this paper, discussion will be made regarding an experiment designed to mimic the aforementioned conditions and how these conditions affected the SIR performance of the no-clean flux residues. A variety of no-clean solder paste flux residues will be discussed, including a halogen-containing, Pb-free solder paste flux; a halogen-free, Pb-free solder paste flux; a halogen-free, Pb-free solder paste flux with a residue optimized for pin probing; and a halogen-free SnPb solder paste flux.
Apex 2011, solder paste, pb-free, halogen-free, no-clean flux, flux residue
[Permanent Link to this Paper ]
Posted on 11 Apr 2011
by Derrick Herron, Dr. Yan Liu, Dr. Ning-Cheng Lee
Quad-flat no-leads (QFN) package designs are receiving more and more attention in the electronics industry. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, the adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints. This is particularly a concern for QFN where the primary function of thermal pads is for heat dissipation. Thermal pad voiding control at QFN assembly is a major challenge due to the large coverage area, large number of thermal via, and low standoff. Both design and process were studied for minimizing and controlling the voiding. Eliminating the thermal via by plugging is most effective in reducing the voiding. For unplugged via situations, a full thermal pad is desired for a low number of via. For a large number of via, a divided thermal pad is preferred due to better venting capability. Placement of a thermal via at the perimeter prevents voiding caused by the via. A wider venting channel has a negligible effect on voiding and reduces joint continuity. For a divided thermal pad, the SMD system is more favorable than the NSMD system, with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing. Performance of a divided thermal pad is dictated by venting accessibility, not by the shape. Voiding reduction increases with increasing venting accessibility, although the introduction of a channel area compromises the continuity of the solder joint. Reduced solder paste volume causes more voiding. Short profiles and long hot profiles are most promising in reducing the voiding. Voiding behavior of a QFN is similar to typical SMT voiding and increases with pad oxidation and further reflow.
voiding, thermal pad, solder, solder paste, SMT, flux, Apex 2011, QFN assembly
[Permanent Link to this Paper ]
Posted on 11 Apr 2011
