Papers about CSP
by Dr. Ning-Cheng Lee , Dr. Benlih Huang, William Manning, Dr. Yan Liu
Voiding is attributed to the flux outgassing within the solder joints when the solder is at molten state. The effect of reflow profile on voiding at microvia for lead-free soldering is strongly dependent on the flux chemistry. In general, wetting is more important than
melting outgasing behavior, and can be enhanced by employing a higher melting energy, including both higher peak temperature and longer dwell time. Use of a high soaking energy can help drying out volatiles hence reduce the melting outgasing and result in low
voiding, but may also increase oxidation for pastes with poor oxidation resistance and cause a high voiding. Testing oxidation resistance of solder paste beforehand will promise a more accurate selection of soaking energy.
pb-free, soldering, BGA, CSP, void, voiding, SMT, solder, lead-free, microvia, profile, reflow
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Posted on 2 Mar 2010
by Dr. Ning-Cheng Lee
In this article, the interconnect infrastructure for SMT, BGA, and
flip chip are reviewed, with particular emphasis on the bonding technology. Interconnection technologies are the vital part of electronic packaging. Obviously, interconnections of SMT industry, from components to boards to board-level assembly methods, are the most mature and well established technology. BGA, on the other hand, intelligently utilizes the knowledge of SMT interconnections and re-engineers the design through combining the strength of various interconnect technologies and successfully comes up with a great family of versatile packages. Flip chip interconnects, while also trying to incorporate existing technology, place a good deal of emphasis on the polymeric systems, and very much develop a new arena of interconnect concepts and processes. The impact of flip chip interconnect progress is expected to ripple through the rest of electronic industries in the near future.
SMT, BGA, Flip Chip, CSP, Interconnection, surface mount, ball grid array, Packaging, assembly, soldering, pb-free, lead-free
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Posted on 1 Jan 2009
by Dr. Ning-Cheng Lee
Lead-free soldering , originally started as an environmental issue, is evolving rapidly into a business survival tool for the worldwide electronic industry. Promising lead-free solder alternatives for surface mount assembly applications include eutectic Sn/Ag, eutectic Sn/Cu, Sn95/Sb5, eutectic Sn/Bi, Sn/Ag/Cu, Sn/Ag/Cu/X, Sn/Bi/Ag/X, Sn/Zn/X, and Sn/In/Ag/(X). However, for wafer level area array solder bump interconnects, most of those options fall short in terms of fatigue resistance. Sn/In/Ag/(X) appears to be superior when compared with Sn63/Pb37, as demonstrated by Sn/In/Ag/Cu. For applications involving high lead solders, no solder alternatives have been developed yet. While the industry is advancing toward being finer, smaller, lighter, and faster, wafer level packages using area array solder interconnects is suffering from the soft error due to alpha emission from the lead in the solders. Although lead-free solder alternatives for eutectic Sn/Pb are virtually free from alpha emission, the continuous dependence on the use of high-lead solders for C4 applications indicates that the challenge of alpha emission from lead-containing solders will persist regardless of the lead-free move of the industry. This challenge is getting tougher with the rapid advancement of IC design toward further miniaturization. Low alpha lead can be obtained from cold lead ore, old lead, and laser isotope separation process, with the latter having potential as a long term solution. The price of those low alpha lead is very expensive when compared with the regular lead. Due to the increase in I/O density, requirement on alpha emission level may soon move from LC2 to LC3 level. The supply of low alpha lead for wafer level interconnects does not seem to be an issue.
lead-free, solder, soldering, wafer level interconnect, Flip Chip, CSP, BGA, alpha emission, low alpha solders, soft error, indium, pb-free
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Posted on 1 Jan 2009
by Dr. Benlih Huang, Dr. Ning-Cheng Lee
Several unique solder paste systems have been developed and tested for 63Sn/37Pb solder bumping for wafer, CSP, and BGA with the low cost print-detach-reflow process. The results indicate that the bump height achieved is very adequate and consistent for all three area array package systems. Microstructure of solder bumps appears normal. The yield is also very high for both before reflow and after reflow condition, and is dictated by printing performance. With the unique high slump resistance exhibited by those newly developed pastes, the paste transfer efficiency at printing stage becomes the most critical performance for this process. The transfer efficiency increases with increasing area ratio, increasing taper angle, decreasing pitch, decreasing stencil thickness, decreasing challenge, with adoption of square aperture design, and is not sensitive to aspect ratio of aperture to solder particle size. The paste systems appear to have more potential for depositing a larger amount of paste per unit pitch, as evidenced by the linear relation between expected paste volume and the deposited paste volume. Increasing metal content helps improving bumping performance. The bottleneck of increasing bumping performance for wafer applications appears to be developing a stencil manufacturing technology capable of providing an aperture pattern with spacing considerably smaller than the stencil thickness. Slow print speed is also essential for adequate printing. A non-shiny non-smooth stencil surface is considered beneficial for aiding paste rolling. The flux residue of those pastes is cleanable with solvents.
solder, soldering, area array package, Flip Chip, BGA, CSP, sphere, Bumping, paste, flux, fluxless, pb-free, lead-free
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Posted on 1 Jan 2009
by Dr. Ning-Cheng Lee , William Casey
Soldering is the primary interconnection technology for area array packages. Methods for solder bumping for area array packages can be categorized as follows: (1) build-up process, (2) liquid solder transfer, (3) solid solder transfer, and (4) solder paste bumping. The first group includes both evaporation and electroplating processes, while the second group includes meniscus bumping and solder jetting. The third group includes wire bumping, sphere welding, decal solder transfer, tacky dot solder transfer, integrated preform, and pick and-place solder transfer processes, with the last one (pick & place solder transfer) being the current prevailing option. Solder paste bumping exhibits great potential to reduce bumping costs dramatically, and includes the print-detach-reflow, print- reflow-detach, and dispense approaches. For an area array package attachment process, depending on the type of packaging, either flux, fluxless soldering or solder paste printing may be used as the attachment medium. Although area array packaging generally offers a robust process, attention should be paid to reduce defects such as delamination, misalignment, elongated joint, voiding, bridging, opens, cracking, poor wetting and various attachment interactions.
lead-free, pb-free, solder, soldering, area array package, Flip Chip, BGA, CSP, sphere, Bumping, paste, flux, fluxless
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Posted on 10 Mar 2010
by Dr. Ning-Cheng Lee , Dr. Yan Liu, Pamela Fiacco
Head-in-pillow (HIP) is ailing the electronic industry when assembling BGAs or CSPs onto PCBs. It is caused by warpage of components or boards at reflow process, and is aggravated by oxidation. Methods for assessing the potential for occurrence of HIP are highly desired by the industry. Besides using BGA rework station followed by tedious dye and pry treatment, two other simpler methods are introduced in this work, Tiny Dot Paste method and Ball Onto Paste method. The Tiny Dot Paste method is stressed on the assessment of oxidation barrier capability of solder paste, while Ball Onto Paste method assesses combined capability of oxidation resistance and excessive fluxing capacity. Both methods are quick, easy, and close simulation, with the latter being better in real process simulation. Prevention of HIP can be accomplished by (1) designing packages without warpage, (2) printing more paste, (3) dipping solder paste or flux, (4) using inert reflow atmosphere, (5) reducing reflow temperature, (6) placing heat shield on BGA or CSP, (7) avoiding using water soluble solder paste for BGA bumped with no-clean process, (8) using solder bumps or solder powder with oxidation resistant alloy, (9) using fluxes with high oxidation barrier capability and high fluxing capacity. Among all options listed above, using solder paste with high oxidation barrier capability and high fluxing capacity is considered the most easily implemented approaches.
head-in-pillow, solder, soldering, reflow, SMT, solder paste, BGA, CSP
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Posted on 24 Jan 2011
