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Indium Corporation conducts extensive research on the soldering fundamentals for Surface Mount Technology and other electronics applications.

Browse our library for abstracts of some of the most popular published articles that you may find useful in your efforts to improve your process results. All papers in our library are available for download.

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    Papers about CTE mismatch

  • A Room Temperature, Low-Stress Bonding Process to Reduce the Impact of Use Stress on a Sputtering Target Assembly

    by Amanda Hartnett, Jacques Matteau, Ronnie Spraker, Omar Knio

    As semiconductor processing has moved to 300mm wafers, the size of deposition targets, including tungsten, tantalum, and molybdenum has grown, and process complexity has increased as well. This added size and complexity contributes to the stress on a target assembly during the physical vapor deposition (PVD) process, and the target assembly’s ability to withstand this stress has a large effect on the resulting deposition rates, yields, and film properties. One of the major sources of stress is the coefficient of thermal expansion (CTE) mismatch between metal targets in semiconductor processes, such as tungsten (CTE of 4.5*10-6/°C), tantalum (6.5*10-6/°C), and molybdenum (5.1*10-6/°C) compared with their backing plates, which are typically made of aluminum (23*10-6/°C), brass (21.2*10-6/°C), or copper-chrome (17.6*10- 6/°C). Standard soldering and solid state joining processes have difficulty controlling stress produced by the CTE-mismatch. We will demonstrate how the NanoBond® process can be used to control stresses during the bonding and deposition processes. Modeling will be conducted to compare standard bonding processes to the NanoBond process, accounting for CTE mismatches.

    SVC Tech Con 2011, NanoFoil, NanoBond, sputtering target, CTE mismatch

    Posted on 19 Apr 2011

  • Room Temperature LED and D-Pak Type Component-Attach and Reliability Testing

    by Mario Scalzo, Thomas Acchione

    Engineers working with LED and D-pak type component-attach are looking for improved assembly materials and process enhancements to increase throughput, reduce cost, and improve product efficiency and reliability. Many of these packages are susceptible to higher voiding on the ground plate-attach during reflow. A room temperature process would lower voiding, reduce the failure rate, and increase the lifetime of the component. Technology developments have proven that it is possible to use a localized heat source to bond components at room temperature. This paper discusses the bonding of LED and D-pak components at room temperature. It also talks about the quality and long term reliability of the components. The presentation will demonstrate the component bonding process both manually and through the use of automation, and show attendees how to verify the performance of the components post bonding.

    NanoFoil, NanoBond, LED, CTE mismatch, room temperature bonding

    Posted on 24 Jan 2011

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