The continual miniaturization of electronics components for personal electronics devices, coupled with the conversion to RoHS- and REACH-compliant lead-free assemblies, has put a tremendous strain on the electronics assembly industry. Introduction of 01005 passives, and active components on the order of 0.3mm pitch, initiates newly defined questions about specification limits for solder paste stencil print performance.
This paper discusses variability of solder paste print performance and its relationship to specification limits. The objective is to describe analyses to determine stencil print process character, using actual paste print measurement data. Aside from setting specification limits, application of statistical methods for the analysis of variation in stencil print performance could help understand appropriate production statistical process control (SPC) limits sought by SMT manufacturing and quality engineers from stencil print inspection results that are gathered during SMT assembly.
Effects on values of Cp and Cpk by various specification limits are presented. This discussion is based on recent application development experiments, to elucidate how average solder paste measurement and standard deviation measurement effect new print process capability challenges. From this work, a strategy to optimize a new 01005 stencil printing process is reviewed. Importantly, the discussion includes key factors with planning quality aspects of SMT assembly. SPC techniques presented will show how to measure stencil print performance capability, and result in opportunity for reduced assembly costs and increased sales income.
transfer efficiency, process capability study, capability ratio, statistical process control (SPC), control charts, stencil aperture design, pad design, solder paste, area ratio
