Experiencing soldering defects? Need help with your SMT electronics assembly process? There's a tool for that.
Statistical tools, like the Ishikawa Diagram, help map out a process and provide an excellent visual aid that helps show the potential defect causes and the effects the process variables can have. These diagrams are often used to help discover the root cause of an issue by understanding all of the variables that could be causing it. At the Indium Corporation we have created a number of Cause and Effect Diagrams over the years. Ed Briggs wrote about one that he put together for Solder Paste Printing Transfer Efficiency. Brandon Judd authored a post depicting the Variables in the Package-on-Package Process. We have produced many diagrams over the years, but I noticed that we didn't have one on QFN Voiding.
A customer contacted me recently, needing to reduce voiding under his QFNs and DPAKs. To help him start thinking about the variables that could be contributing to his large voiding percentages, I created an Ishikawa diagram for QFN/Large Ground Plane Voiding. You'll see it depicted in the image, above. Even though there can be thousands of variables affecting a particular process, and even though any diagram could be wildly complex, it is best to start with the most common variables. In this customer's particular scenario we were able to help them reduce their voiding with stencil design changes - including stencil thickness and aperture design. However, we are still working with them to optimize other variables to decrease voiding even further.
In any DOE it is always important to change one variable at a time and to document your work so that you know if, and to what degree, each change affects the process. Also, if the change causes a negative impact on the process, your documented work will allow you to go back to the previous settings.
Stay tuned for future discussions that will help you AVOID THE VOID™.