In a previous post I spoke about Large Ground Plane Voiding in Electronics Assembly and referred to a statistical tool called an Ishikawa Diagram. This tool helps map out a process and provide an excellent visual aid that helps show the potential defect causes and the effects the process variables can have. This particular Ishikawa Diagram showed that PWB Design can have a large effect on voiding. Today I will dig into this area a bit further and talk about how we can minimize large ground plane solder voiding in electronic assembly with differences in PWB Design.
Printed Wiring Board (PWB) design can have a tremendous effect on BTC voiding. Vias in the thermal pads are often times added to the board to aid in heat dissipation. Sometimes these vias are filled or buried - which have less of an effect on voiding. Many times it is too costly to fill the vias and, although through-hole vias may provide a channel for flux volatiles to escape, the size and shape of the via may increase BTC voiding. For example, we have found, in certain instances where large through-hole vias are present in the thermal ground pads, that voiding increases. In this scenario the solder paste present on the ground pad tends to wick down into the via during reflow. This tends to suck the component down closer to the board, reducing the standoff height which makes it tougher for the flux volatiles to outgas properly. This is similar to the effect of stencil thickness on BTC voiding that I have discussed in a previous post on the effect of stencil design on BTC voiding. The result would typically be higher BTC voiding.
Many designs do not have vias present, and the pad size and shape along with the ratio between the board pad and the component pad would have more of an effect on the BTC voiding in this scenario. These variables can also have an effect on thermal pads with vias as well. If the board thermal pad is larger than the component thermal pad, the solder paste would tend to wet out on the pad more and this could also reduce the standoff of the component resulting in greater BTC voiding.
There are some designs that introduce solder mask on the pads to control standoff, reduce the size of the pad, or provide an outgassing channel. These designs can aid in BTC voiding reduction if designed properly for the specific component and application. Derrick Herron, Dr. Yan Liu, & Dr. Ning-Cheng Lee authored a great paper on this subject entitled QFN Voiding Control Via Solder Mask Patterning on Thermal Pads.
Stay tuned for my next discussion on how reflow profiles can affect voiding under bottom-terminated components.