Indium Corporation’s Dr. Andy Mackie, Senior Product Manager, Semiconductor and Advanced Assembly Materials, and Sze Pei Lim, Regional Manager, Semiconductor, discuss when to make the move from water-soluble to no-clean fluxes, and the factors that go into making that decision.
Andy: Sze Pei, we've talked about flip-chip flux over the years with our customers. Is there really a clear boundary of when customers should move from water-soluble to no-clean, particularly the ultra-low residue fluxes?
Sze Pei: It depends on a lot of things and also the design of the package itself. We used to just have maybe one or two flip-chip on the system-in-package, but now we are packing up to 20 flip-chip in just a tiny package. So,the pitch is getting smaller. It used to be solder bump, which is big, and now its become copper-pillar and even micro-pillar, so the pitch has gone down to maybe 40 microns, 30 microns, and maybe even 20 microns .
As the pitch goes further down, of course water having that high surface tension its going to be difficult to really penetrate into those tight gaps and get rid of all the residue. There will be a point where our customers have to look at the ultra-low residue, no-clean flip-chip flux. So, I would say probably around that range of 40 microns to 30 microns kind of pitch.
And of course, it also depends on the size of the die. If the die is small, even though with a very tight pitch, you may still be able to clean it off well, all the residue. But if the die is big, to clean the center we make-
Andy Mackie: Very difficult.
Sze Pei Lim: ... More difficult. So, it really depends. Yeah.
Andy Mackie: Okay. So, can you tell us a little bit about the work you're doing with the Consortia, and with the road mapping with heterogeneous integration.
Sze Pei Lim: We participate in one of the consortium, which is led by ASM. We mainly focus on the fan-out wafer level packaging and now we are on our second stage of the project, which we also incorporate fan-out SiP. So, where we have a few die—up to three dies and a couple of passive for the fan-out wafer-level packaging, it is either wafer-level or panel-level, so this is on the fan-out. And then we encapsulate and make it into a package, so we study the whole process from the wafer, the chip itself, and all the way until we finally package it. And then, we also do the reliability on the bottom level.
So, this is what we have been doing and we have a couple papers already being published. I think more than 10 papers. So, you can find out more information from our website as well. We study the process challenges and the materials sets challenges. Warpage is a big challenge. So, that's why all these papers are written based on all these challenges.
Andy Mackie: Okay.
Sze Pei Lim: And for the heterogeneous integration roadmap: Yes, I'm involved in particularly the advanced packaging portion. So, we look at the 3D, the 2.5 D, and also wafer-level packaging. The roadmap should be published soon—at least a draft of it.
Andy Mackie: Has that been pushed out a little bit?
Sze Pei Lim: Yeah, we have been pushed out a couple of times.
Andy Mackie: Okay thanks ever so much.
Andy Mackie: If you'd like to learn more please contact us. And, Sze Pei thank you for your time.
Sze Pei Lim: Thank you, Andy.