Indium Blog

Process Considerations for QFN Voiding in SMT Electronics Assembly (3/3)

Phil Zarrow: This is part three of a three-part series. This video is for anyone interested in Design of Experiment aspect of Avoid the Void™.
Brook, let's talk a little bit about the effect of design variables on voiding. What about the stencil?
Brook Sandy-Smith: Well, the stencil's pretty complicated, Phil.
Phil Zarrow: Right.
Brook Sandy-Smith: It really depends on your pad design. The competent manufacturer usually has a set of guidelines that they give you, either specifying your stencil thickness, or the standoff height that you'd like have under the component after reflow. But they also, in the case of our components that we use, they also recommend putting 38-80% of the area as solder paste.
Phil Zarrow: Yeah. Right.
Brook Sandy-Smith: Just logically, if you're trying to fill the volume of an ideal standoff height, you're not going to have enough solder to do so, so you're inviting in some voiding to begin with.
I ran an experiment where I chose different stencil designs with more solder. In this case, the pad was complete, it didn't have vias. And we tried to target 100% of the ideal volume of solder that you wanted with the standoff height and tried to leave different pathways to let the volatiles escape. Increasing the amount of solder didn't always decrease the average voiding, but it did decrease the variation and sometimes got rid of those outliers, the high-voided components.
Phil Zarrow: How would you summarize your general philosophy towards stencil design with regard to solder past volume on ground planes?
Brook Sandy-Smith: I think that we need to balance the amount of solder that we're putting into the solder joint on the thermal pad with the amount of solder that we have on the signal pad so that we're not bridging or getting excessive or insufficient solder on those joints. Then depending on whether there are vias...
Phil Zarrow: Ah, vias.
Brook Sandy-Smith:... there might be a complicating factor as to what stencil design you might chose.
Phil Zarrow: There are a lot of variables with the vias themselves.
Brook Sandy-Smith: Right. There are different designs, whether they're tented or plugged, or whether the solder can escape down them. These would all influence the amount of solder that you want to put down and the design so that you're not, maybe, putting solder paste directly over an open via.
Phil Zarrow: You've done a lot of exhaustive work. It's a fascinating topic. Where can we find more information, Brook?
Brook Sandy-Smith: For more information, you can find more videos and blogs at or you can contact me directly at
Phil Zarrow: Excellent.