It’s no secret that indium and indium-silver solder thermal interface materials (TIMs) show great potential for maximizing thermal performance in high-performance computing (HPC) and AI applications. Pure indium, specifically, boasts a high bulk thermal conductivity (k = 86W/mK) on its own. Indium-silver alloys commonly used for solder TIMs have a slightly lower thermal conductivity, which is dependent on the silver concentration in the alloy.
Much of the challenge in implementing these materials is defining the soldering process. But before we can even think about a thermal profile and its impact on voiding or reliability, it’s important to use the correct solderable surfaces to ensure a strong, mechanically fastened solder TIM joint.
This blog will cover the current metallization stack-up for indium and indium-silver based materials. With over two decades of development work, there have been multiple iterations of what should go on both the silicon die surface and the heat-sink or integrated heat spreader surface. We will explore what is currently used and how past applications of pure indium have contributed to our current understanding of what makes indium-based soldering so effective.
Why Indium or Indium-Silver Solder TIM?
Before we tackle the metallization stack-up, let’s discuss why indium or indium-silver-based materials are used for TIM1 and TIM1.5 in the AI, data center, and HPC ecosystem. In these applications, there is typically significant warpage associated with the silicon die surface where the TIM is applied. As the die heats and cools during operation, the constant dynamic flexure is caused by the coefficient of thermal expansion (CTE) mismatch between the materials making up the chip.
Pure indium, along with its high bulk thermal conductivity, is also a very compliant, soft metal. It has a very low yield stress and is more subject to creeping and deforming compared to other solder alloys in the solid state. Indium’s mechanical behavior is what separates it from most tin-based solder alloys and graphitic TIMs, as its compliance is critical to the thermomechanical reliability of a finished BGA, LGA, FC, or ASIC device.
What is the Current Recommended Metallization Stack-Up for Solder TIM?
Choosing the correct metallization is always a major question in the SMT space. The stack-up referenced here is our personal recommendation for TIM1 and TIM1.5 usage and assumes the solder TIM will be implemented between a silicon die surface and a copper heat-sink, lid, or integrated heat spreader.
Figure 1: Typical metallization stack-up for solder TIM in a TIM1 or TIM1.5 application.
On the silicon die side, it is typical to see some form of sputtered titanium, nickel-vanadium (NiV), or gold back side metallization (BSM).
- The titanium layer acts as the adhesion layer between the silicon and NiV layers.
- The NiV layer is the solderable layer responsible for the indium-nickel intermetallic compound (IMC) formation. If you are unsure how thick this layer should be, going thicker on the nickel is a safe option.
- Finally, the thin gold layer acts as a passivation layer, preventing oxidation of the solderable NiV layer and promoting a long shelf life before the soldering process. It’s recommended to keep this layer as thin as possible while maintaining its passivation characteristics. Similar to gold-tin embrittlement seen in printed circuit board assembly (PCBA) and surface mount technology (SMT), indium-gold IMCs are extremely brittle. An excess of these IMCs can cause small microcracking at the interface and lead to early mechanical failures.
As for the heat-sink, lid, or integrated heat spreader surface, it’s standard to use some form of electroless nickel plating (nickel-phosphorus (NiP), 5-7% mid phosphorus) or electrolytic nickel plating. A selectively plated immersion gold layer is then applied to either similar dimensions as the silicon die or slightly larger. This is important because the gold layer acts as a “metallurgical solder mask.”
Without applying excessive force to the indium solder TIM during reflow, the molten solder wets to the selectively plated gold surface. Since an interface is already formed with the In2Au intermetallic, the solder is encouraged to continue wetting this surface until the thin gold layer is used up. Figure 2 illustrates this phenomenon.
Figure 2: Left: ENIG-plated copper lid test vehicles with selectively plated immersion gold flash in the center. Right: Indium solder after reflow, removed from the chip. The solder material wet to the gold-plated surface and did not extend out to the nickel-plated surface.
Similar to the silicon die side, it’s recommended to have a thicker nickel layer to form the dominant IMC at the interface and a very thin gold layer to prevent premature mechanical failures. Figure 3 depicts a pure indium solder joint interface using a recommended stack-up. The dominant interface on the nickel surface should be an indium-nickel or indium-nickel-gold IMC. The gold layer should be entirely used up after the reflow process, showing indium-gold IMCs that have diffused into the bulk of the indium solder.
Figure 3: Left: metallization stack-up of a solder TIM dummy test vehicle. Right: cross-section close-up of the interfacial reaction between the indium solder TIM and the ENIG metallization after soldering.
Other Potential Metallization for Indium and Indium-Silver Solder TIMs
The nickel-gold metallization stack-up has plenty of research backing it—over two decades worth, to be exact. It not only works but has been proven on multiple occasions to provide solid thermal cycling and shock reliability. With that said, other potential options for solderable surfaces could help with the wetting characteristics of indium-based solder alloys during reflow.
Indium naturally has a high surface tension in its molten state. Because of this, molten indium would often rather stick to itself than immediately begin forming an intermetallic with the thin solderable gold layer. After the indium has “balled up” (and fluxing or oxide reduction has occurred), it will begin forming an intermetallic with the gold layer. This initial “balling up” phenomenon on gold substrates can sometimes cause unexpected wetting failures when first defining a reflow process.
Indium-silver solder TIM alloys can help with this, but you do lose some ductility and bulk thermal conductivity as a trade-off. That being said, indium is unique from a metallurgical standpoint due to its willingness to diffuse with other materials. For example, some studies depict a readily formed indium-silver IMC formation, not just in the solder TIM space but also in the electroplating of indium over a thick silver layer. Perhaps using thin immersion silver or sputtered silver layers instead of gold could help with indium wetting on large die areas while still maintaining indium-nickel IMCs as the dominant interface. Indium also wets to itself rather easily, so the possibility of using indium metallization for these applications could be explored as well.
Take a Deeper Dive into Solder TIMs
Mastering the intricacies of metallization is just one part of successfully integrating solder TIMs into your high-performance package designs. To explore this topic further and learn how to lessen the learning curve from design to production, register for our upcoming webinar.
Join Kyle Aserian, Applications Development Engineer at Indium Corporation, for “Every Degree Matters: Solder TIMs for Lidded Package Designs (TIM1)” on October 29, 2025, at 2 p.m. EST.
In this session, you will learn about:
- An overview of TIM1 assembly (die-to-lid/integrated heat spreader).
- Process integration and design considerations for solder TIMs.
- The keys to success for a reliable TIM1 solder joint.
- Inspection, characterization, and reliability assessment methodology.
This webinar is ideal for design, process, or NPI engineers looking to integrate high-performance thermal interface materials into LGA, BGA, or other chip-level assemblies.
Save your spot to unlock the true potential of AI, gaming, and high-performance computing. Register now!
Sources:
Deppisch, et al; “The Material Optimization and Reliability Characterization of an Indium-Solder Thermal Interface Material for CPU Packaging”; JOM; June, 2006.
