Since the early days of SMT assembly, one of the most persistent defects with the greatest longevity is voiding in solder joints. Other defects – such as graping, head-in-pillow, and non-wet opens – have known solutions, but voiding remains largely unsolved and with each technology inflection seems to make a strong comeback. The increased use of bottom-terminated components (BTC), high-density electronics, and high-reliability alloys needed for today’s automotive applications has resulted in a renewed focus on voiding reduction. Voiding in solder bumped components (e.g., BGAs and CSPs) and BTCs (including QFNs and DPAK) each have their own unique cause and mitigation techniques. To consistently maintain an acceptable level of voiding per industry standards and self-imposed levels due to stringent in-use requirements, a detailed understanding of the unique causes of voiding and process mitigation techniques is needed. This session will review the cause and effect relationship between voiding and the soldering materials used in today’s electronics assemblies. We will also review material and process solutions to maintain acceptable levels of voiding in various forms of SMT assembly.

Due to changes in the operating conditions of electronic assemblies, new mission profiles are constantly needed for lifetime reliability. These also increase the demands on the materials used in assemblies. In the area of “no-clean” solder pastes, the focus is on the Surface Insulation Resistance (SIR) test as proof of the electrochemical duration reliability of these flux residues. For example, today’s existing test duration has increased from 168 hours to 1,000 hours (+600%). Some flux systems in solder pastes already have solutions to these new challenges.